Arrays in Verilog

ARRAYS :

An array is a collection of similar types of variables and is accessed using the same name plus one or more indexes.

   

An array can be declared as wire, reg, integer, time, real-time, and vector datatype. It can be either scalar or vector.  It can be either single dimension or multi-dimension.

The array dimension is declared by having the max and min indexes in the square brackets. An array can be declared in both directions.

Representation of array for single dimension :

1. array_name [most_significant_index:least_significant_index];

2. array_name [least_significant_index:most_significant_index];

Example of array representation for single dimension:

1. fifo [8:0];

2. fifo [0:8];

Single dimension array data allocation:

In array the data is allocated in vertical pattern.

For example:

1. fifo [9:0];

2. fifo [0:9];

Representation of array for two dimensional array:

1. array_name [most_significant_index:least_significant_index][most_significant_index:least_significant_index];

2. array_name [most_significant_index:least_significant_index][least_significant_index:most_significant_index];

3. array_name [least_significant_index:most_significant_index][most_significant_index:least_significant_index];

4. array_name [least_significant_index:most_significant_index][least_significant_index:most_significant_index];

Example of array representation for two dimensional array:

1. fifo [8:0][2:0];

2. fifo [8:0][0:2];

3. fifo [0:8][2:0];

4. fifo [0:8][2:0];

Two dimensional array data allocation:

For example:

1. fifo [3:0][1:0];

2. fifo [3:0][0:1];