Logic Gates Program using Gate Level Modeling

 Logic Gates:

Logic gates are the deify model of the computation, which implements the Boolean function. The logic gates help us to perform the logic operation on one or more inputs to produce the single binary output.

There are 7 basic logic gates they are 

1. AND Gate.
2. OR Gate.
3. NOT Gate.
4. NAND Gate.
5. NOR Gate.
6. XOR Gate.
7. XNOR Gate.

The NAND Gate and NOR Gate are known as universal gates, any gates can be constructed by using these two gates.

1. AND GATE SYMBOL AND TRUTH TABLE:

    AND gate will perform an operation of (A.B). This means the output will be '1' if and only both the inputs are '1'  otherwise '0'.

2. OR GATE SYMBOL AND TRUTH TABLE:

    OR gate will perform an operation of (A+B). This means the output will be '1' if any one input is '1'  otherwise '0'.

3. NOT GATE SYMBOL AND TRUTH TABLE:

    NOT gate will perform an operation of (~A). This means the output will be the complement of the input.

4. NAND GATE SYMBOL AND TRUTH TABLE:

    

    NAND gate will perform the complement operation of AND Gate which is ~(A.B). This means the output will be '1' for all inputs except when both inputs are '1'.

5. NOR GATE SYMBOL AND TRUTH TABLE:

    NOR gate will perform the complement operation of  OR Gate which is ~(A+B). This means the output will be '1' if and only if both inputs are '1' otherwise '0'.

6. XOR GATE SYMBOL AND TRUTH TABLE:

    XOR gate will perform an operation of ((~(A)).B) + (A.(~B))). This means the output will be '1' if and only one input is '1'  otherwise '0'.

7. XNOR GATE SYMBOL AND TRUTH TABLE:

    XNOR gate will perform an operation of ((~(A.B)) + (A.B)). This means the output will be '1' if and only both inputs are the same otherwise '0'.

PROGRAM:

CODE:

This program is coded and simulated using ModelSim software. The program contains the primitives of gate which are and, or, not, nand, nor, xor, xnor. 

The syntax for writing logic gate using primitive is:

Gate primitive(output, input);

Example for AND Gate:

and(t,a,b);  // where a,b are inputs and t is output

module gate_level(input a,b, output t,u,v,w,x,y,z);

  

  and(t,a,b);

  or(u,a,b);

  not(v,a);

  nand(w,a,b);

  nor(x,a,b);

  xor(y,a,b);

  xnor(z,a,b);

endmodule 

TESTBENCH:

The test bench is used to test the code using the test case. The below test bench code is a linear test bench code. 

module gate_level_testbench;

  

  reg A,B;

  wire T,U,V,W,X,Y,Z;

  

  gate_level dut(.a(A), .b(B), .t(T), .u(U), .v(V), .w(W), .x(X), .y(Y), .z(Z));

  

  initial 

  begin 

    

    A = 0; B = 0;

    #10 A = 0; B = 1;

    #10 A = 1; B = 0;

    #10 A = 1; B = 1;

    

  end

endmodule

OUTPUT WAVEFORM:

The below output is simulated using the Modelsim. The output is based on the testbench written above.