Arrays in Verilog

ARRAYS :

An array is a collection of similar types of variables and is accessed using the same name plus one or more indexes.

   

An array can be declared as wire, reg, integer, time, real-time, and vector datatype. It can be either scalar or vector.  It can be either single dimension or multi-dimension.

The array dimension is declared by having the max and min indexes in the square brackets. An array can be declared in both directions.

Representation of array for single dimension :

1. array_name [most_significant_index:least_significant_index];

2. array_name [least_significant_index:most_significant_index];

Example of array representation for single dimension:

1. fifo [8:0];

2. fifo [0:8];

Single dimension array data allocation:

In array the data is allocated in vertical pattern.

For example:

1. fifo [9:0];

2. fifo [0:9];

Representation of array for two dimensional array:

1. array_name [most_significant_index:least_significant_index][most_significant_index:least_significant_index];

2. array_name [most_significant_index:least_significant_index][least_significant_index:most_significant_index];

3. array_name [least_significant_index:most_significant_index][most_significant_index:least_significant_index];

4. array_name [least_significant_index:most_significant_index][least_significant_index:most_significant_index];

Example of array representation for two dimensional array:

1. fifo [8:0][2:0];

2. fifo [8:0][0:2];

3. fifo [0:8][2:0];

4. fifo [0:8][2:0];

Two dimensional array data allocation:

For example:

1. fifo [3:0][1:0];

2. fifo [3:0][0:1];

Moore state Machine of 101 verilog program

The Moore state machine is a finite state machine whose output values depend on the current state.

The Moore state machine output will have the n+1 states for n inputs. For example, if the input has 3 states then it will produce 4 output states.

THE MOORE STATE MACHINE OF 11:

The Moore state machine for 101. It has four states S0, S1, S2, S3. The output will be '1' when it enters state S3 and the outputs of the remaining state are '0'.

PROGRAM:

// The inputs and outputs are declared here

module moore_sequence_101(input CLK,RST,DIN, output reg DOUT);

  

  parameter [1:0]S0 = 2'b00;

  parameter [1:0]S1 = 2'b01;

  parameter [1:0]S2 = 2'b10;

  parameter [1:0]S3 = 2'b11;

  

  reg [1:0] PS;

  reg [1:0] NS;

 // Moore state machine is designed using asynchronous

  

  always @(posedge CLK or negedge RST)

  begin

    if(RST)

      PS <= S0;

    else

      PS <= NS;

  end

  

  always @(PS,DIN)

  begin

    case(PS)

      

// For the state S0

      S0:if(DIN)

          begin

            NS = S1;

            DOUT = 1'b0;

          end

       else

         begin

            NS = S0;

            DOUT = 1'b0;

         end

      

// For the state S1

      S1:if(DIN)

          begin

            NS = S1;

            DOUT = 1'b0;

          end

        else

         begin

            NS = S2;

            DOUT = 1'b0;

         end

        

// For the state S2

      S2:if(DIN)

          begin

            NS = S3;

            DOUT = 1'b0;

          end

         else

           begin

             NS = S0;

            DOUT = 1'b0;

           end

        

// For the state S3

      S3:if(DIN)

          begin

            NS = S1;

            DOUT = 1'b1;

          end

        else

          begin

            NS = S2;

            DOUT = 1'b1;

          end

    

    endcase

  end

endmodule

OUTPUT WAVEFORM:

The output values are tested by forcing the input manually.

when the CLK input is high, rst is low, and based on din the output will be high. When the rst pin is high the output will be zero.

The input is given as 0,0,1,0,1,1,0.

Moore state Machine of 11 verilog program

The Moore state machine is a finite state machine whose output values depend on the current state.

The Moore state machine output will have the n+1 states for n inputs. For example, if the input has 2 states then it will produce 3 output states.

THE MOORE STATE MACHINE OF 11:

The Moore state machine for 11. It has three states S0, S1, S2. The output will be '1' when it enters to state S2 and the remaining state outputs are '0'.

PROGRAM:

// The inputs and outputs are declared here

module moore_sequence_11(input CLK,RST,DIN, output reg DOUT);

  

 parameter [1:0]S0 = 2'b00;

 parameter [1:0]S1 = 2'b01;

 parameter [1:0]S2 = 2'b10;

 

 reg [1:0]PS;

 reg [1:0]NS;

 

 // Moore state machine is designed using asynchronous

 always @(posedge CLK or negedge RST)

  begin

    if(RST)

      PS <= S0;

    else

      PS <= NS;

  end

    

  always @(PS, DIN)

  begin

    case(PS)

   

// For the state S0

   

      S0:if(DIN)

          begin

            NS = S1;

            DOUT = 1'b0;

          end

        else

        begin

          NS = S0;

          DOUT = 1'b0;

        end

// For the state S1

            

      S1:if(DIN) 

          begin

            NS = S2;

            DOUT = 1'b0;

          end

      else

        begin

            NS = S0;

            DOUT = 1'b0;

        end

// For the state S2

               

      S2:if(DIN)

          begin

            NS = S1;

            DOUT = 1'b1;

          end

        else

          begin

            NS = S0;

            DOUT = 1'b1;

          end

          

    endcase

  end   

endmodule 

OUTPUT WAVEFORM:

The output values are tested by forcing the input manually.

when the CLK input is high, rst is low, and based on din the output will be high. When the rst pin is high the output will be zero.

The input is given as 0,0,1,1,1,0.

Logic Gates Program using Gate Level Modeling

 Logic Gates:

Logic gates are the deify model of the computation, which implements the Boolean function. The logic gates help us to perform the logic operation on one or more inputs to produce the single binary output.

There are 7 basic logic gates they are 

1. AND Gate.
2. OR Gate.
3. NOT Gate.
4. NAND Gate.
5. NOR Gate.
6. XOR Gate.
7. XNOR Gate.

The NAND Gate and NOR Gate are known as universal gates, any gates can be constructed by using these two gates.

1. AND GATE SYMBOL AND TRUTH TABLE:

    AND gate will perform an operation of (A.B). This means the output will be '1' if and only both the inputs are '1'  otherwise '0'.

2. OR GATE SYMBOL AND TRUTH TABLE:

    OR gate will perform an operation of (A+B). This means the output will be '1' if any one input is '1'  otherwise '0'.

3. NOT GATE SYMBOL AND TRUTH TABLE:

    NOT gate will perform an operation of (~A). This means the output will be the complement of the input.

4. NAND GATE SYMBOL AND TRUTH TABLE:

    

    NAND gate will perform the complement operation of AND Gate which is ~(A.B). This means the output will be '1' for all inputs except when both inputs are '1'.

5. NOR GATE SYMBOL AND TRUTH TABLE:

    NOR gate will perform the complement operation of  OR Gate which is ~(A+B). This means the output will be '1' if and only if both inputs are '1' otherwise '0'.

6. XOR GATE SYMBOL AND TRUTH TABLE:

    XOR gate will perform an operation of ((~(A)).B) + (A.(~B))). This means the output will be '1' if and only one input is '1'  otherwise '0'.

7. XNOR GATE SYMBOL AND TRUTH TABLE:

    XNOR gate will perform an operation of ((~(A.B)) + (A.B)). This means the output will be '1' if and only both inputs are the same otherwise '0'.

PROGRAM:

CODE:

This program is coded and simulated using ModelSim software. The program contains the primitives of gate which are and, or, not, nand, nor, xor, xnor. 

The syntax for writing logic gate using primitive is:

Gate primitive(output, input);

Example for AND Gate:

and(t,a,b);  // where a,b are inputs and t is output

module gate_level(input a,b, output t,u,v,w,x,y,z);

  

  and(t,a,b);

  or(u,a,b);

  not(v,a);

  nand(w,a,b);

  nor(x,a,b);

  xor(y,a,b);

  xnor(z,a,b);

endmodule 

TESTBENCH:

The test bench is used to test the code using the test case. The below test bench code is a linear test bench code. 

module gate_level_testbench;

  

  reg A,B;

  wire T,U,V,W,X,Y,Z;

  

  gate_level dut(.a(A), .b(B), .t(T), .u(U), .v(V), .w(W), .x(X), .y(Y), .z(Z));

  

  initial 

  begin 

    

    A = 0; B = 0;

    #10 A = 0; B = 1;

    #10 A = 1; B = 0;

    #10 A = 1; B = 1;

    

  end

endmodule

OUTPUT WAVEFORM:

The below output is simulated using the Modelsim. The output is based on the testbench written above.